Ratified Extensions

Load/Store Pair for RV32 (Zilsd & Zclsd)

Zilsd, Zclsd

The RISC-V Debug Specification

Sdext, Sdtrig

RISC-V Control Transfer Records

Smctr, Ssctr

RISC-V Pointer Masking

Smmpm, Smnpm, Ssnpm, Supm, Sspm

The RISC-V Instruction Set Manual Volume II: Privileged Architecture 

Sm1p13, Ss1p13

Double Trap

Ssdbltrp, Smdbltrp

RISC-V Quality-of-Service (QoS) Identifiers

Ssqosid

Obviating Memory-Management Instructions after Marking PTEs Valid

Svvptc

Resumable Non-Maskable Interrupts

Smrnmi

Shadow Stacks and Landing Pads

Zicfiss, Zicfilp

BF16 Extensions

Zfbfmin, Zvfbfmin, Zvfbfwma

Zaamo and Zalrsc Extensions

Zaamo, Zalrsc

B Standard Extension for Bit Manipulation Instructions

B

Byte and Halfword Atomic Memory Operations (Zabha)

Zabha

RISC-V Supervisor Counter Delegation

Smcdeleg, Ssccfg

May-Be-Operations

Zimop, Zcmop

RISC-V Indirect CSR Access (Smcsrind/Sscsrind)

Smcsrind, Sscsrind

RISC-V Integer Conditional (Zicond) operations extension

Zicond

Hardware Updating of PTE A/D Bits (Svadu)

Svadu

RISC-V Cycle and Instret Privilege Mode Filtering (Smcntrpmf)

Smcntrpmf

Atomic Compare-and-Swap (CAS) Instructions (Zacas)

Zacas

RISC-V Cryptography Extensions Volume II: Vector Instructions

Zvbb, Zvbc, Zvkb, Zvkg, Zvkn, Zvknc, Zvkned, Zvkng, Zvknha, Zvknhb, Zvks, Zvksc, Zvksed, Zvksg, Zvksh, Zvkt

"Zfa" Standard Extension for Additional Floating-Point Instructions

Zfa

RISC-V Advanced Interrupt Architecture

Smaia, Ssaia

“Zvfh/Zvfhmin:” Vector Extension for Half-Precision Floating-Point Arithmetic/Vector Extension for Minimal Half-
Precision Floating-Point Arithmetic

Zvfh, Zvfhmin

“Zihintntl” Non-Temporal Locality Hints

Zihintntl

RISC-V Code Size Reduction

Zca, Zcb, Zcd, Zce, Zcf, Zcmp, Zcmt

RISC-V Profiles

RVA20, RVI20, RVA22

"Zicntr" and "Zihpm" Counters

Zicntr, Zihpm

RV32E and RV64E Base Integer Instruction Sets

RV32E/RV64E

“Ztso” Standard Extension for Total Store Ordering

Ztso

RISC-V Wait-on-Reservation-Set (Zawrs) extension

Zawrs

Zmmul Extension

Zmmul

PMP Enhancements for memory access and execution prevention on Machine mode (Smepmp)

Smepmp

RISC-V Base Cache Management Operation ISA Extensions

Zicbom, Zicbop, Zicboz

RISC-V Bit-Manipulation ISA-extensions

Zba, Zbb, Zbc, Zbs

RISC-V Count Overflow and Mode-Based Filtering Extension

Sscofpmf

RISC-V Cryptography Extensions Volume I: Scalar & Entropy Source Instructions

Zbkb, Zbkc, Zbkx, Zknd, Zkne, Zknh, Zksed, Zksh, Zkn, Zks, Zkt, Zk, Zkr

RISC-V State Enable Extension

Smstateen

RISC-V "stimecmp / vstimecmp" Extension

Sstc

RISC-V Vector Extension

Zve32x, Zve32f, Zve64x, Zve64f, Zve64d, Zve, Zvl32b, Zvl64b, Zvl128b, Zvl256b, Zvl512b, Zvl1024b, Zvl, Zv

The RISC-V Instruction Set Manual Volume II: Privileged Architecture 

Sm1p12, Ss1p12, Sv57, Hypervisor, Svinval, Svnapot, Svpbmt

"Zfh" and "Zfhmin" Standard Extensions for Half-Precision Floating-Point

Zfh, Zfhmin

"Zfinx", "Zdinx", "Zhinx", "Zhinxmin": Standard Extensions for Floating-Point in Integer Registers

Zfinx, Zdinx, Zhinx, Zhinxmin

“Zihintpause” Pause Hint

Zihintpause

The RISC-V Instruction Set Manual Volume I: Unprivileged ISA

A, D, F, RV32I, RV64I, Zaamo, Zalrsc, Zicsr, Zifencei

The RISC-V Instruction Set Manual Volume II: Privileged Architecture 

C, M, Q, Sm1p11, Ss1p11, Sv32, Sv39, Sv48